Two main types of FETs that presently exist are: JFETs and MOSFETs.
MOSFETs can be further classified into depletion type and enhancement type. Both these types define the fundamental mode of operation of MOSFETs, while the term MOSFET itself is the abbreviation of metal-oxide-semiconductor-field-effect transistor.
Due to the fact that the two types have different working characteristics, we'll be evaluating each of them separately in different articles.
In this present article we'll discuss the depletion type MOSFET, which are said to have characteristics matching that of a JFET. The similarity is between cut-off and saturation near IDSS.
However, MOSFETs have more enhanced characteristic which enters as far as the region opposite of VGS polarity.
Fig.5.23 shows the basic internal structure of a n-channel depletion-type MOSFET.
We can find a block of p-type material created using a silicon base. This block is called the substrate.
The substrate is the base or the foundation over which a MOSFET is constructed. For some MOSFETs it is internally linked with the "source" terminal. Also, many devices offer an extra output in the form of SS, featuring a 4-terminal MOSFET, as revealed in Fig.5.23
The drain and the source terminals are connected through conductive contacts to n-doped locations, and attached through an n-channel, as indicated in the same figure.
The gate is also connected to a metallic layer, although it is insulated from the n-channel through a fine layer of silicon dioxide (SiO2).
SiO2 possesses a unique form of insulation property called dielectric which creates an opposing electric field within itself in response to an externally applied electric field.
Being an insulating layer, the material SiO2 offers us the following important information:
A complete isolation is developed between the gate terminal and the mosfet channel with this material.
Moreover, it is because of SiO2, the gate of the mosfet is able to feature an extremely high degree of input impedance.
Due to this vital high input impedance property, the gate current IG is virtually zero amps for any dc-biased MOSFET configuration.
Basic Operation and Characteristics
AS can be seen in Fig.5.24, the gate to source voltage has been configured at zero volts by connecting the two terminals together, while a voltage VDS is applied across the drain and source terminals.
With the above setting, the drain side establishes a positive potential by the n-channel free electrons, along with an equivalent current through the JFET channel. Also, the resulting current VGS = 0V is still being identified as IDSS, as given in Fig. 5.25
We can see that in Fig.5.26 the gate source voltage VGS is given a negative potential in the form of -1V.
This negative potential tries to force electrons toward the p-channel substrate (since charges repel), and pull holes from the p-channel substrate (since opposite charges attract).
Depending on how large this negative bias VGS is, a recombination of holes and electrons takes place which results in the reduction of free electrons in the n-channel available for the conduction. Higher levels of negative bias results in higher rate of recombination.
The drain current consequently is reduced as the above negative bias condition is increased, which is proven in Fig.5.25 for VGS levels of VGS = -1, -2 and so forth, until the pinch-off mark of -6V.
The drain current as a result along with the transfer curve plot proceeds just like that of a JFET.
Now, for the positive VGS values, the gate positive will attract excess electrons (free carriers) from the p-type substrate, on account of the reverse leakage current. This will establish fresh carriers by the way of resultant collisions across the accelerating particles.
As the gate-to-source voltage tends to rise at the positive rate, the drain current shows a rapid increase, as proven in the Fig.5.25 for the same reasons as discussed above.
The gap developed between the curves of VGS = 0V and VGS = +1 distinctly shows the amount by which the current increased due to the 1 - V variation of the VGS
Due to the fast rise of the drain current we must be careful about the maximum current rating, otherwise it could cross the positive gate voltage limit.
For example, for the device type depicted in the Fig.5.25, applying a VGS = +4V would cause the drain current to rise at 22.2 mA, which may be crossing the maximum breakdown limit (current) of the device.
The above condition shows that the use of a positive gate-to-source voltage generates an enhanced effect on the quantity of the free carriers in the channel, as opposed to when VGS = 0V.
This is why the positive gate voltage region on the drain or transfer characteristics is generally known as enhancement region. This region lies between the cut-off and the saturation level of IDSS or the depletion region.
Solving an Example Problem
p-Channel Depletion-Type MOSFET
The construction of a p-channel depletion-type MOSFET is a perfect reverse of an n-channel version shown in Fig.5.23. Meaning, the substrate now takes the form of an n-type and the channel becomes a p-type, as can be seen in Fig.5.28a below.
The terminal identification remains unchanged, but the voltage and the current polarities are reversed, as indicated in the same figure. The drain characteristics would be exactly as depicted in Fig.5.25, except VDS sign which will in this case get a negative value.
The drain current ID shows a positive polarity in this case too, that's because we have already reversed its direction. VGS shows an opposite polarity, which is understandable, as indicated in Fig.5.28c.
Because VGS is reversed produces a mirror image for the transfer characteristics as indicated in Fig.5,28b.
Meaning, the drain current increases in the positive VGS region from the cut-off point at VGS = Vp until IDSS, then it continues to rise as the negative value of VGS rises.
The graphical signs for an n- and p-channel depletion-type MOSFET can be witnessed in the above Fig. 5.29.
Observe the way the selected symbols aim to represent the true structure of the device.
The absence of a direct interconnection (because of the gate insulation) between the gate and channel is symbolized by a gap between the gate and the different terminals of the symbol.
The vertical line which represents the channel is attached between the drain and source and is “held” by the substrate.
Two groups of symbols are furnished in the figure above for each type of channel to highlight the fact that in some devices the substrate may be accessible externally while in others this may not be seen.
In our next tutorial we will talk about enhancement-type mosfet.