Although depletion type and enhancement type MOSFETs look similar with their internal structures and functional mode, their characteristics may be quite different.
The main difference being the drain current which depends on a specific level of gate-to-source voltage for the cut off action.
Precisely, for an n-channel enhancement-type MOSFET a positive gate/source voltage effects its working, instead of a range of negative potentials which can normally impact a depletion type MOSFET.
You can visualize the n-channel enhancement-type MOSFET in the following
A p-type material section is created through a silicon base, and as learned before it is termed as the substrate.
This substrate on some occasions is attached internally with the source pin in a depletion-type MOSFET, while in some instances it is terminated as a fourth lead for enabling an external control of its potential level.
The source and drain terminals are as usual joined using metallic contacts to n-doped regions.
However, it may be important to visualize that in Fig. 5.31 the channel between the two n-doped regions is missing.
This may be considered as the fundamental dissimilarity between a depletion-type and an enhancement-type MOSFET's internal layout, that is an absence of an inherent channel which is supposed to be a part of the device.
The SiO2 layer can be seen still prevalent, which ensures an isolation between the metallic base of the gate terminal and the region between the drain and source. However, here it can be witnessed standing separated from the p-type material section.
From the above discussion we can conclude that a depletion and enhancement MOSFET internal layout may have some similarities, except the missing channel between drain/source for an enhancement type of MOSFET.
Basic Operation and Characteristics
For an enhancement type MOSFET when a 0 V is introduced at its VGS, due to the missing n-channel (which is known to carry a lot of free carriers) causes a current output to be zero, which is quite unlike of a depletion type of MOSFET, having ID = IDSS.
In such a situation due to a missing path across drain/source terminals, large amounts of carriers in the form of electrons are unable to accumulate at drain/source (because of the n-doped regions).
Applying some positive potential at VDS, with VGS set at zero volts and the SS terminal shorted with the source terminal, we actually find a couple of reverse biased p-n junctions between the n-doped regions and the p-substrate to enable any notable conduction across drain to source.
In Fig. 5.32 shows a condition where VDS and VGS are applied with some positive voltage higher than 0 V, allowing the drain and gate to be at a positive potential with respect to the source.
The positive potential at the gate pushes the holes in the p-substrate along the edge of the SiO2 layer departing the location and entering deeper into the regions of the p-substrate, as shown in the above figure. This happens because of the like charges that repel each other.
This results in a depletion region being created close to the SiO2 insulating layer that is void of holes.
Despite of this, the p-substrate electrons which are the minority carriers of the material are pulled towards the positive gate and start gathering in the region close to the surface of the SiO2 layer.
Due to the insulation property of the SiO2 layer negative carriers allow the negative carriers from getting absorbed at the gate terminal.
As we increase the level of VGS, the electron density close to the SiO2 surface also increase, until finally the induced n-type region is able to allow a quantifiable conduction across drain/source.
The VGS magnitude that causes an optimal increase in the drain current is termed as the threshold voltage, signified by the symbol VT. In datasheets you will be able to see this as VGS(Th).
As learned above, due to the absence of a channel at VGS = 0, and "enhanced" with the positive gate-to-source voltage application, this type of MOSFET are known as enhancement-type MOSFETs.
You will find that both depletion- and enhancement-type MOSFETs exhibit enhancement-type regions, but the term enhancement is used for the latter because it specifically works using an enhancement mode of operation.
Now, when VGS is pushed over the threshold value, the concentration of the free carriers will boost in the channel where it's induced. This causes the drain current to increase.
On the other hand, if we keep the VGS constant and increase the VDS (drain-to-source voltage) level, this will ultimately cause the MOSFET to reach its saturation point, as normally would also happen to any JFET or a depletion MOSFET.
As shown in Fig. 5.33 the drain current ID gets leveled off with the aid of a pinching-off process, indicated by the narrower channel towards the drain end of the induced channel.
By applying applying Kirchhoff’s voltage law to the MOSFET's terminal voltages in Fig. 5.33, we get:
If VGS is kept constant to a specific value, for example 8 V, and VDS is raised from 2 to 5 V, the voltage VDG by Eq. 5.11 could be seen dropping from -6 to -3 V, and the gate potential getting less and less positive with respect to the drain voltage.
This response prohibits the free carriers or electrons from getting pulled towards this region of the induced channel, which in turn results in a drop in the effective width of the channel.
Ultimately, the channel width decreases to the point of pinch-off , reaching a saturation condition similar to what we already learned in our earlier depletion MOSFET article.
Meaning, increasing the VDS any further with a fixed VGS does not affect the saturation level of ID, until the point where a breakdown situation is reached.
Looking at the Fig 5.34 we can identify that for a MOSFET as in Fig.5.33 having VGS = 8 V, saturation takes place at a VDS level of 6 V. To be precise the VDS saturation level is associated to the applied VGS level by:
No doubt, it thus implies that when the VT value is fixed, increasing the level of VGS will proportionately cause higher levels of saturation for VDS through the locus of saturation levels.
Referring to the characteristics shown in the above figure, the VT level is 2 V, which is evident by the fact that the drain current has fallen to 0 mA.
Therefore typically we can say:
When VGS values are less than the threshold level for enhancement-type MOSFET, its drain current is 0 mA.
We can also clearly see in the above figure that as long as the VGS is raised higher from VT to 8 V, the corresponding saturation level for ID also increases from 0 to 10 mA level.
Moreover we can further notice that the space between the VGS levels increases with an increase in the value of VGS, causing an infinitely rising increments in drain current.
We find the drain current value is related to the gate-to-source voltage for VGS levels that's greater than VT, through the following nonlinear relationship:
The term which is shown squared bracket is the term which is responsible for the nonlinear relatinship between ID and VGS.
The term k is a constant and is a function of the MOSFET layout.
We can find out the value of this constant k through the following equation:
where the ID(on) and VGD(on) each are values specifically depending on the characteristic of the device.
In the next Fig. 5.35 below we find the drain and transfer characteristics are arranged one beside the other to clarify the transfer process across one another.
Basically, it is similar to the process explained previously for JFET and depletion-type MOSFETs.
However, for the present case we have to remember that the drain current is 0 mA for VGS VT.
Here ID may see a noticeable amount of current, which will increase as determined by Eq. 5.13.
Note, while defining the points over the transfer characteristics from the drain characteristics, we only consider the saturation levels. This restricts the region of operation to VDS values higher than the saturation levels as established by Eq. (5.12).
p-Channel Enhancement-Type MOSFETs
The structure of a p-channel enhancement-type MOSFET as shown in Fig. 5.37a is just the opposite of that showing up in Fig. 5.31.
Meaning, , now you find that an n-type substrate and p-doped regions beneath the drain and source joints.
The terminals continue to be as established, but each of the current directions and the voltage polarities are reversed.
The drain characteristics can look like as given in Fig. 5.37c, having increasing amounts of current caused by a continuously more negative magnitudes of VGS.
The transfer characteristics would be the mirror impression (around the ID axis) of the transfer curve of Fig. 5.35, having ID increasing with more and more negative values of VGS above VT, as displayed in Fig. 5.37b. Equations (5.11) through (5.14) are similarly appropriate to p-channel devices.