The following post describes an H-bridge modified sine wave inverter circuit using four n-channel mosfets. Let's learn more about the circuit functioning.
The H-Bridge Concept
We all know that among the different inverter typologies, the H-bridge is the most efficient one, since it does not necessitate the use of center tap transformers, and allows the use of transformers with two wires. The results become even better when four N-channel mosfets are involved.
With a two wire transformer connected to an H-bridge means the associated winding is allowed to go through the push pull oscillations in a reverse forward manner. This provides better efficiency as the attainable current gain here becomes higher than the ordinary center tap type topologies.
However better things are never easy to get or implement. When identical type mosfets are involved in an H-bridge network, driving them efficiently becomes a big problem. It is primarily due to the following facts:
As we know an H-bridge topology incorporates four mosfets for the specified operations. With all four of them being N-channel types, driving the upper mosfets or the high side mosfets becomes an issue.
This is because during conduction the upper mosfets experience almost the same level of potential at their source terminal as the supply voltage, due to the presence of the load resistance at the source terminal.
That means the upper mosfets come across similar voltage levels at their gate and source while operating.
Since as per the specs, the source voltage must be close to the ground potential for efficient conduction, the situation instantly inhibits the particular mosfet from conducting, and the entire circuit stalls.
In order to switch the upper mosfets efficiently they must be applied with a gate voltage at least 6V higher than the available supply voltage.
Meaning if the supply voltage is 12V, we would require at least 18-20V at the gate of the high side mosfets.
Using 4 N-Channel Mosfets for the Inverter
The proposed H-bridge inverter circuit having 4 n channel mosfets tries to overcome this problem by introducing a higher voltage bootstrapping network for operating the high side mosfets.
N1, N2, N3, N4 NOT gates from the IC 4049 are arranged as a voltage doubler circuit, which generates about 20 volts from the available 12V supply.
This voltage is applied to the high side mosfets via a couple NPN transistors.
The low side mosfets receive the gate voltages directly from the respective sources.
The oscillating (totem pole) frequency is derived from a standard decade counter IC, the IC 4017.
We know that the IC 4017 generates sequencing high outputs across its specified 10 output pins. The sequencing logic shuts subsquently as it jumps from one pin to the other.
Here all the 10 outputs are used so that the IC never gets a chance of producing incorrect switching of its output pins.
The groups of three outputs fed to the mosfets keep the pulse width to reasonable dimensions. The feature also provides the user the facility of tweaking the pulse width that's being fed to the mosfets.
By reducing the number of outputs to the respective mosfets, the pulse width can be effectively reduced and vice versa.
This means the RMS is tweakable here to some extents, and renders the circuit a modified sine wave circuit ability.
The clocks to the IC 4017 is taken from the bootstrapping oscillator network itself.
The oscillating frequency of the bootstrapping circuit is intentionally fixed at 1kHz, so that it becomes applicable for driving the IC4017 also, which ultimately provides about 50 Hz output to the connected 4 N-channel H bridge inverter circuit.
The proposed design can be much simplified as given here:
Using P Channel and N Channel MOSFETs
The next simple full bridge or half-bridge modified sine wave inverter was also developed by me. The idea incorporates 2 P channel, and 2 n channel mosfets for the H-bridge configuration and effectively implements all the necessary functions flawlessly.
IC 4049 pinouts
How the Inverter Circuit is Configured Stage-wise
The circuit may be basically divided into three stages, viz. The oscillator stage, the driver stage and the full bridge mosfet output stage.
Looking at the shown circuit diagram, the idea can be explained with the following points:
IC1 which is the IC555 is wired in its standard astable mode, and is responsible for generating the required pulses or the oscillations.
The values of P1 and C1 determines the frequency and the duty cycle of the generated oscillations.
IC2 which is a decade counter/divider IC4017, performs two functions: optimization of the waveform and providing a safe triggering for the full bridge stage.
Providing a safe triggering for the mosfets is the most important function which is performed by IC2. Let's learn how it's implemented.
How the IC 4017 is Designed to Work
As we all know the the output of IC4017 sequences in response to each rising edge clock applied at its input pin#14.
The pulses from IC1 initiates the sequencing process such that the pulses jump from one pin out to the other in the following order: 3-2-4-7-1. Meaning, in response to the fed each input pulse the output of the IC4017 will become high from pin#3 to pin#1 and the cycle will repeat as long as the input at Pin#14 persists.
Once the output reaches pin#1 it's reset via pin#15, so that the cycle can repeat back from pin#3.
At the instant when pin#3 is high, nothing conducts at the output.
The moment the above pulse jumps to pin#2 it becomes high which switches ON T4 (N-channel mosfet responds to positive signal), simultaneously transistor T1 also conducts, it's collector goes low which at the same instant switches ON T5, which being a P-channel mosfet responds to the low signal at T1's collector.
With T4 and T5 ON, current passes from the positive terminal through the involved transformer winding TR1 across to the ground terminal. This pushes the current through TR1 in one direction (from right to left).
At the next instant, the pulse jumps from pin#2 to pin#4, since this pinout is blank, once again nothing conducts.
However when the sequence jumps from pin#4 to pin#7, T2 conducts and repeats the functions of T1 but in the reverse direction. That is, this time T3 and T6 conduct switching the current across TR1 in the opposite direction (from left to right). The cycle completes the H-bridge functioning successfully.
Finally, the pulse jumps from the above pin to pin#1 where it's reset back to pin#3 and the cycle keeps repeating.
The blank space at pin#4 is the most crucial, as it keeps the mosfets entirely safe from any possible "shoot through" and ensures a 100% flawless functioning of the full bridge avoiding the need and involvement of complicated mosfet drivers.
The blank pinout also helps to implement the required typical, crude modified sine wave-form, as shown in the diagram.
The transfer of the pulse across the IC4017 from its pin#3 to pin#1 constitutes one cycle, which must repeat 50 or 60 times in order to generate the required 50 Hz or 60 Hz cycles at the output of TR1.
Therefore multiplying the number of pinouts by 50 gives 4 x 50 = 200 Hz. This is the frequency that must be set at the input of IC2 or at the output of IC1.
The frequency may be easily set with the help of P1.
The proposed full bridge modified sine wave inverter circuit design may be modified in numerous different ways as per individual preferences.
Does the mark space ratio of IC1 have any effect on the pulse features?....thing to ponder about.
R2, R3, R4, R5 = 1K
R1, P1, C2 = needs to be calculated at 50Hz using this 555 IC calculator
C2 = 10nF
T1, T2 = BC547
T3, T5 = IRF9540
T4, T6 = IRF540
IC1 = IC 555
IC2 = 4017
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