I/V Tracker Circuit for Solar MPPT Applications

Optimizing power by tracking is the key feature which makes solar MPPT concept so unique and efficient, where the complex and non-linear I/V curve of the solar panel is tracked and switched for creating maximum optimal conditions for the connected load.

The Circuit Concept

I have been trying hard to design something that would in true sense track the I/V curve or the power curve of the panel, and correct it automatically whenever it drifts from the optimal points.The proposed design is based on the same grounds, but here I have included only the I (current) tracking stage in order to keep things simple. Actually it's the current that really matters and is directly proportional to power of the panel so I thought keeping this parameter in control could fulfill the job.

Let's try to understand the design with the following observations:

How the Circuit Functions

Looking at the proposed solar MPPT I/V curve tracker circuit diagram, the BC547 at the extreme right along with the 10k resistor and 1uF capacitor forms a linear ramp generator.

The central stage comprising the two 555 ICs form a variable PWM controlled output generator, while the IC 741 stage becomes the actual current tracker stage.

When the voltage from the solar panel connects across the BC547 collector and ground, due to the presence of the base 10k/1uf network, the emitter follower provides a gently rising voltage to the 555 PWM generator stage.

The ramp activates IC2 and forces it to generate a correspondingly rising PWM output at its pin#3 which goes to the gate of the driver mosfet.

The mosfet responds to these pulses and gradually increases its conduction and provides current to the battery in the same incremental order.

As soon as the current intake across the battery begins rising, an equivalent voltage level is translated across the current sensing resistor Rx which gets applied a pin#3 of the 741 IC.

The above potential also hits pin#2 of 741 via the dropping 1N4148 diode so that pin#2 follows this potential in tandem with pin#3 but lags behind by about 0.6V due to the presence of the series diode.

The above condition allows the opamp to begin with a high output which keeps the diodes at its pin#6 reverse biased.

As long as the current keeps climbing with the ramp, opamp pin#3 continues to be higher than pin#2, thus keeping the output higher.

However at some point of time, which might be after the I/V curve has just crossed, the current output from the panel starts dropping or rather drops abruptly across Rx.

This is sensed by pin#3 immediately, however due to the presence of the 33u capacitor, pin#2 is unable to sense and follow this drop in potential.

The above situation instantly forces the pin#3 voltage to become lower than pin#2, which in turn reverts the output of the IC to zero, forward biasing the connected diode.

The base of the ramp generator BC547 is dragged to zero forcing it to switch OFF, and reset the whole procedure back to the original state. The process now begins afresh.

The above procedure continues and ensures that the current is never allowed to fall or cross the inefficient region of the I/V curve.

This is just an assumption, a concept which I have tried to implement, it might require a lot many tweaking and alignments before it can become truly result oriented.

The output from the mosfet may be integrated with an SMPS based converter for even higher efficiency.