In this article we learn how to use NAND Gates from the IV 4093 or any other similar IC consisting of NAND gates.
About IC 4093
The IC 4093 may not have complicated specifications and attributes yet it proposes many useful utilities. It consists of some fundamental blocks which can be configured according to personal preferences and used for numerous different applications.
Externally the IC 4093 looks quite an ordinary dual in line type of IC.
It consists of 14 pins and has four CMOS blocks internally embedded inside its package.
These blocks are called gates, here these are termed NAND gates.
Understanding and using NAND gates of IC 4093 is simple and there’s nothing complicated about these gates.
Just think them as an electronic component having a couple of inputs and a single output, quite like a transistor, but these gates are embedded inside a package and are not individual components like transistors.
However the above explained gates are entirely different with their characteristics compared to linear devices like transistors.
The gates are simply made to produce specified sets of output voltages in response to the particular specified sets of input voltage commands.
Consider a single NAND gate having two inputs and a single output.
Provide a positive voltage to both the inputs; you get a negative voltage at the output pin.
Apply negative or ground voltages to booth the inputs and you get a positive voltage at the output.
Applying opposite voltage levels at the input pins produces no effect on the output and it stays positive with its voltage.
The information tells us about the logical property of the gate that is for a NAND gate, and is generally given in the form of truth tables.
It is important thing to note that the inputs should always be applied with definite voltage levels and cannot be left open.
The output pin may be normally used for triggering the next stage in an electronic circuit, however it does not carry any criticality and will not damage the IC if left open.
Another issue with the inputs is that the applied voltage should never exceed the supply voltage to the IC which in turn should be within the specified range, normally within 5 to 15 volts.
Undefined voltage levels according to CMOS gates are within 0.75 and 2.5 volts. Anything above 2.5 is considered to be logic 1 or logic high and anything below 0.75 is considered to be a logic 0 or a logic low.