In this article we learn how to use NAND Gates from the IV 4093 or any other similar IC consisting of NAND gates.
About IC 4093
The IC 4093 may not have complicated specifications and attributes yet it proposes many useful utilities. It consists of some fundamental blocks which can be configured according to personal preferences and used for numerous different applications.
Externally the IC 4093 looks quite an ordinary dual in line type of IC.
It consists of 14 pins and has four CMOS blocks internally embedded inside its package.
These blocks are called gates, here these are termed NAND gates.
Understanding and using NAND gates of IC 4093 is simple and there’s nothing complicated about these gates.
You can imagine them as an electronic component having a couple of inputs and a single output, quite like a transistor, but these gates are embedded inside a package and are not individual components like transistors.
However the above explained gates are entirely different with their characteristics compared to linear devices like transistors.
The gates are simply made to produce specified sets of output voltages in response to the particular specified sets of input voltage commands.
Consider a single NAND gate which will have two inputs and a single output.
Provide a positive voltage to both the inputs; you get a negative voltage at the output pin.
Apply negative or ground voltages to both the inputs and you get a positive voltage at the output.
Applying opposite voltage levels at the input pins produces no effect on the output and it stays positive with its voltage.
The information tells us about the logical property of the gate that is for a NAND gate, and is generally given in the form of truth tables.
It is important thing to note that the inputs should always be applied with definite voltage levels and cannot be left open.
Absolute Maximum Rating
The following ratings indicate the maximum and the minimum values that must not be exceeded while using the IC 4093, under any circumstances, to avoid permanent damage to the IC
- VDD Supply voltage at pin#14 = -0.5 to +22V
- VI DC input voltage = -0.5 to VDD + 0.5
- II DC input current = ±10 mA
- PD Power dissipation per package = 200 mW
- PD Power dissipation per output transistor = 100 mW
- Top Operating temperature -55 to +125°C
- Tstg Storage temperature -65 to +150
How to Use
The IC 4093 may be used depending on the truth table functions, and the working of the gate outputs in response to gate input logics, or voltages.
The output pin may be normally used for triggering the next stage in an electronic circuit, however it does not carry any criticality and will not damage the IC if left open.
However, the applied voltage to the inputs of the gates should never exceed the supply voltage to the IC which in turn should be within the specified range, normally within 2 to 15 volts.
Undefined voltage levels according to CMOS gates are within 0.75 and 2.5 volts. Anything above 2.5 is considered to be logic 1 or logic high and anything below 0.75 is considered to be a logic 0 or a logic low.
What is Schmitt Trigger
Although the functioning of IC 4093 is exactly same as any ordinary NAND gate, and even the truth table figures are exactly identical, yet the IC 4093 is referred to as schmitt trigger. Why?
It is because, the IC 4093 gate output response to an input signal lags with a small time delay, which ensures that the output is never influenced by accidental, or stray input signal variations, rather the output response are created only to genuine input signals. This function happens due to the internal hysteresis effect attribute of the IC.
For example, suppose a very short momentary pulse is applied to the gate input, which may be just around the threshold of a genuine input logic pulse level.
Such pulses will be ignored by the 4093 schmitt trigger gates, since the slight delay in the output response will cause the gate to wait until the signal is detected to be above the correct thresholds. In this situation the output of the gate will remain stable and unchanged.
The gate output status will change state only once a genuine input pulse is detected, which remains consistently high or low, for the hysteresis delay margin of the gate.