The post analyzes a solar charger circuit which includes an I/V tracking feature for implementing an efficient battery charging operations.
A solar panel as we all know is used for converting sun rays into electricity, however when a disproportionate load is connected with a solar panel its efficiency could get reduced drastically making the entire system highly inefficient.
An flyback converter when connected in between the load and solar panel makes sure that the load acquires the optimal amount of energy without distorting the efficiency of the solar panel.
Basically a solar panel is just another power supply whose efficiency invariably depends on the use of its current(amps) correctly.
As per the I/V tracking graph of a solar panel, we see that for so long as the voltage is not disturbed (dropped) the panel operates over its maximum power point zone, where it is able to supply its maximum rated current to the load.
In other words if the available maximum voltage of the panel is not bogged down by the load the panel continues to supply the optimal range of current to the connected load. This parameter becomes solely crucial with any solar panel, and a flyback topology specifically takes care of this when applied with a solar panel a load.
Conversely, it can be also assumed that since the voltage is simply a function of the current, as long as the amps from the solar panel is extracted to an optimal point, the voltage doesn't get affected thereby holding the operations within the optimal zone. This is exactly what's been implemented in the discussed design.
The proposed flyback solar charger circuit with I/V tracking is designed by me keeping in mind the above criticality of a solar panel.
How the I/V Tracker is Designed to Work
Let's learn the details of the circuit by referring to the following diagram below:
Here the IC 741 section is the current tracking stage, the IC555 are configured as PWM optimizer while the BC547 stage is for generating an incrementing ramp.
When the circuit is powered up with a solar panel, the ramp generator starts producing a ramping voltage across pin5 of IC2 (555).
IC2 along with IC1 converts this ramping voltage into correspondingly rising PWMs at a given high frequency.
This PWM is applied to a ferrite transformer primary winding via a N-channel mosfet.
The output of the ferrite transformer is appropriately filtered and integrated with the load or a battery which needs to be charged.
As the ramp and the corresponding PWM climbs, the battery starts acquiring the required current.
This current (amp) intake rate by the battery is applied to the inputs of the I/V tracking IC741 opamp stage in the form of a rising voltage across Rx.
The voltage across Rx is detected and monitored by the inputs of the opamp.
While it rises pin2 receives a voltage that's about 0.6V lower than that at pin3.
This keeps the opamp output pin6 high during the initial ramping operations, and only as long as the current ramp does not drop.
The moment the current consumption goes above the optimal range, the voltage across Rx begins to drop, which is reflected at pin3 of the opamp.
However pin2 at this instant is unable to respond to the above change due to the charge stored inside the 33uF which latches the "current-knee" equivalent level at pin2.
Now as the current drops further, after a difference of 0.6V pin3 potential starts getting lower than pin2 of the opamp.
The above condition immediately reverts the opamp pin6 into a low logic.
The low logic at pin6 now does two executions simultaneously.
It grounds the base of the BC547 transistor, forcing the ramp voltage to begin afresh from zero so that the entire procedure is restored to the start preventing the solar voltage from dropping.
It also makes sure that the 33uF cap discharges for the next ramp cycle.
The cycle thus keeps switching and restoring the situation ensuring that the system does not draw current above the rated point. This in turn holds the voltage of the solar panel at its maximum specified open circuit level.
Together, the I/V knee is never allowed to distort toward the inefficiency zone of the panel.
The discussed circuit is only at its assumed level and could require too many refinements until it actually becomes a practically feasible design. It's not yet tested by me.