The circuit may be basically divided into three stages, viz. The oscillator stage, the driver stage and the full bridge mosfet output stage.
Looking at the shown circuit diagram, the idea can be explained with the following points:
IC1 which is the IC555 is wired in its standard astable mode, and is responsible for generating the required pulses or the oscillations.
The values of P1 and C1 determines the frequency and the duty cycle of the generated oscillations.
IC2 which is a decade counter/divider IC4017, performs two functions: optimization of the waveform and providing a safe triggering for the full bridge stage.
Providing a safe triggering for the mosfets is the most important function which is performed by IC2. Let's learn how it's implemented.
As we all know the the output of IC4017 sequences in response to each rising edge clock applied at its input pin#14.
The pulses from IC1 initiates the sequencing process such that the pulses jump from one pin out to the other in the following order: 3-2-4-7-1. Meaning, in response to the fed each input pulse the output of the IC4017 will become high from pin#3 to pin#1 and the cycle will repeat as long as the input at Pin#14 persists.
Once the output reaches pin#1 it's reset via pin#15, so that the cycle can repeat back from pin#3.
At the instant when pin#3 is high, nothing conducts at the output.
The moment the above pulse jumps to pin#2 it becomes high which switches ON T4 (N-channel mosfet responds to positive signal), simultaneously transistor T1 also conducts, it's collector goes low which at the same instant switches ON T5, which being a P-channel mosfet responds to the low signal at T1's collector.
With T4 and T5 ON, current passes from the positive terminal through the involved transformer winding TR1 across to the ground terminal. This pushes the current through TR1 in one direction (from right to left).
At the next instant, the pulse jumps from pin#2 to pin#4, since this pinout is blank, once again nothing conducts.
However when the sequence jumps from pin#4 to pin#7, T2 conducts and repeats the functions of T1 but in the reverse direction. That is, this time T3 and T6 conduct switching the current across TR1 in the opposite direction (from left to right). The cycle completes the H-bridge functioning successfully.
Finally, the pulse jumps from the above pin to pin#1 where it's reset back to pin#3 and the cycle keeps repeating.
The blank space at pin#4 is the most crucial, as it keeps the mosfets entirely safe from any possible "shoot through" and ensures a 100% flawless functioning of the full bridge avoiding the need and involvement of complicated mosfet drivers.
The blank pinout also helps to implement the required typical, crude modified sine wave-form, as shown in the diagram.
The transfer of the pulse across the IC4017 from its pin#3 to pin#1 constitutes one cycle, which must repeat 50 or 60 times in order to generate the required 50 Hz or 60 Hz cycles at the output of TR1.
Therefore multiplying the number of pinouts by 50 gives 4 x 50 = 200 Hz. This is the frequency that must be set at the input of IC2 or at the output of IC1.
The frequency may be easily set with the help of P1.
The proposed full bridge modified sine wave inverter circuit design may be modified in numerous different ways as per individual preferences.
Does the mark space ratio of IC1 have any effect on the pulse features?....thing to ponder about.
R2, R3, R4, R5 = 1K
R1, P1, C2 = needs to be calculated at 50Hz using this 555 IC calculator
C2 = 10nF
T1, T2 = BC547
T3, T5 = IRF9540
T4, T6 = IRF540
IC1 = IC 555
IC2 = 4017