The following image shows the package of the chip, which looks like a 10 pin DIL IC, the various pinout functions of the same may be studied from the data as furnished under the diagram:
Referring to the circuit diagram of the proposed sensorless BLDC driver circuit as presented in the previous article and also the chip image above, the pinouts details may be understood as follows:
FG = It is the motor speed indicator pin (output), which is rigged in an open collector mode with an internal BJT.
Open collector signifies that the output at this pinout will produce the negative PWMs through sinking logics across the open collector and ground, thus to get a valid reading the user will need to connect a pull up resistor across this open collector and the positive supply (5V) for accomplishing the speed indication at this pinout.
FGS = It's the speed indicator selector input, meaning a logic high or low may be introduced here for switching ON/OFF the indicator pin FG.
Vcc = The positive supply to the IC for enabling it to operate, must not exceed 5V.
W, U and V are the 3-phase outputs for the BLDC motor which is supposed to be operated through this IC. This also acts like inputs for sensing the motor EMF pulses for the required synchronized switching of the motor coils.
GND = Refers to the negative supply pinout of the IC with respect to Vdd pin.
FR = Helps to select or command the direction of the motor and may be dynamically changed anytime once the system is powered, simply by introducing an external logic high or logic low.
PWM = It signifies the PWM control input from an external PWM waveform generator.
This PWM input may be variable for implementing the desired speed control of the connected BLDC motor.
The dotted space at the center of the chip indicates the thermal pad, which may be clamped or pressed with a heatsink in order to sink the possible heat generation on the chip while its being used with a loaded BLDC motor.
The above discussion states the pinout or the connection details of the sensorless BLDC motor driver chip DRV10963, now let's analyze the internal configuration and functioning of the chip in detail with the help of the following points:
The DRV10963 is a 3 phase
sensorless electric motor operator with built-in power MOSFETs (3-phase H-bridged). It is
tailored for higher productivity, reduced noise and minimal secondary
material count motor drive functions. The exclusive sensorless
window-Iess 180° sinusoidal management scheme delivers noise-free motor
The DRV10963 made up of an smart lock
detect functionality, put together with supplementary in-built security
circuits to achieve secured performance. The DRV10963 can be found in a
thermally efficient 10- pin USON packing with an uncovered thermal mat.
In depth Explanation
The DRV10963 product is a 3 phase sensorless motor operator with infused power MOSFETs, It is
created specifically for superior performance, reduced resonance and minimum superficial part count motor drive functions.
principal sensorless window-less 180° sinusoidal control plan presents
noiseless motor functioning by maintaining electrically stimulated
torque ripple nominal.
Upon initialization, the DRV10963 device is going to turn the motor in the course specified through the FR input pin.
The DRV10963 chip is going to function a 3 phase BLDC motor making use of a sinusoidal control plan.
significance of the employed sinusoidal phase voltages depends upon the
duty cycle of the PWM pin. While the motor moves, the DRV10963 IC
delivers the velocity data at the FG pin.
unit consists of a smart lock sense capability. In the event like that
in which the motor is stunted by an extraneous pressure, the program is
going to identify the locking problem and will take measures to
safeguard on its own along with the motor.
The particular procedure of the lock sense circuit is depicted in detail in Lock Detection.
DRV10963 IC furthermore includes multiple in-built safety circuits for
example over current protection, over voltage protection, under voltage
protection, and over temperature protection.
Speed Input and Control
DRV10963 presents 3-phase 25-kl-lz PWM outputs which may have a
standard percentage of sinusoidal waveforms from phase to phase. In case
any cycle is determined with regards to ground, the waveform detected
are likely to be a PWM protected sinusoid combined with 3rd order
harmonics as shown in Figure 2.
This coding strategy
streamlines the driver specifications for the reason that there will
probably often be one phase output that could be on par with zero.
outcome amplitude varies according to the supply voltage (VCC) and the
mandated PWM duty cycle (PWM) as defined in Equation 1 and highlighted
in Figure 3. The optimum amplitude is implemented once the instructed
PWM duty cycle is 100 PERCENT.
Vphpk = PWMdc > < VCC
motor speed is regulated not directly through the use of the PWM order
to regulate the amplitude of the phase voltages that happen to be used
for the motor.
The duty cycle of PWM input is modified into a 9 bit digital quantity (from 0 to 511).
regulation resolution is 1/512 == 0.2%. The duty cycle analyzer
facilitates an initial order exchange operation amongst the input duty
cycle and the 9 bits digital figure.
This is highlighted in Figure 4, in which r=80 ms.
exchange performance between the PWM ordered duty cycle along with the
output maximum amplitude is variable in the DRV10963 device.
outcome maximum amplitude is discussed by Equation 1 when PWM command
> minimum functioning duty cycle. The lowest operation duty cycle
often is established to possibly 13%, 10%, 5% or no restriction by OTP
Table 1 demonstrates the
recommended configurations for the minimal operation duty cycle.
Whenever the PWM instructed duty cycle is less than lowest functioning
duty cycle and more than 1.5%, the output is going to be regulated at
the minimal operation duty cycle. Any time the input duty cycle is under
a 1.5%, the DRV10963 device will likely not run the output, and is sent
to the standby mode.
This can be illustrated in Figure 6.
DRV10963 will start the motor by means of a technique that is finely detailed in Figure 7.
motor initialization graph consists of device configurable alternatives
for open loop to close loop changeover limit (HOW.), align time
(TAHQH), and accelerate rate (RACE).
To line up the
rotor to the commutation logic the DRV10963 executes an x% duty cycle on
phases V and W at the same time controlling phase U at GND.
scenario is sustained for TAIign seconds. The x% significance is
identified by the VCC voltage (as shown in Table 2) to keep up ample
rotational torque over various different supply voltages.
the align sequence accomplishes, the motor is forced to speed up by
putting on sinusoidal phase voltages with peak levels as illustrated in
Table 2 and boosting by means of the commutation range at an expanding
rate represented by RACE until the level of commutation grows to Hom.,
AS soon as this limit is arrived at, the DRV‘l0963
converts to closed loop mode whereby the commutation drive progression
is recognized by the in-built control algorithm while the employed
voltage is identified by the PWM mandated duty cycle input.
open loop to close loop changeover limit (Hom), align time (TAHQH), and
the accelerate rate (RACE) are configurable through OTP configurations.
selection of handoff threshold (HOW,) are typically approved by trial
and error assessment. The objective would be to prefer a handoff
tolerance that could be as little as feasible and enables the motor to
effortlessly and faithfully changeover between the open loop
acceleration and the closed loop acceleration.
increased speed motors (maximum speed) necessitate a superior handoff
tolerance due to the fact elevated speed motors comprise decreased Kt
hence more affordable BEMF.
Table 3 demonstrates the
configurable preferences for the handoff tolerance. Highest speed in
electrical Hz are proven as a reference to help out with choosing the
desirable handoff speed for a specific submission.
The choice of align time (TAHQH) and accelerate rate (RACE) can even be contingent on trial and error examination.
with greater inertia normally demand an extended align time and a more
sluggish speed up rate in contrast to motors with low inertia that
commonly demand a briefer align time together with a speedier accelerate
percentage. Program tradeoffs needs to be implemented to capitalize on
launch stability as opposed to rotate up period.
endorses starting with deciding on the less intense configurations
(slower RACE and significant Tmign) to compromise the torque up time in
support of maximum fulfillment rate.
As soon as the
equipment is confirmed to perform conscientiously the extra forceful
configurations (greater RACC and lesser TAHQH) may be used to diminish
the turn up moment and at the same time cautiously keeping track of the
Table 4 exhibits the configurable settings for TA"g,, and RACE.
The remaining part of the explanation regarding this sensorless BLDC IC is furnished in this original datasheet
Please feel free to comment to know more regarding the above discussed sensorless BLDC motor driver circuit details