The main features of this specialized capacitive touch and proximity sensor can be studies as given below:
The following image shows the internal configuration of the IC PCF8883
The IC doesn't rely on the traditional dynamic capacitance mode of sensing rather detects the variation in the static capacitance by employing automatic correction through continuous auto-calibration.
The sensor is basically in the form of a small conductive foil which may be directly integrated with the relevant pinouts of the IC for the intended capacitive sensing or perhaps terminated to longer distances through coaxial cables for enabling accurate and effective remote capacitive touch sensing operations
The following figures represent the pinout details of the IC PCF8883. The detailed functioning of the various pinouts and the in-built circuitry may be understood with the following points:
A typical application configuration can be studied through this capacitive touch/proximity sensorcircuit design
The pinout IN which is supposed to be connected with the external capacitive sensing foil is linked with the ICs internal RC network.
The discharge time given by "tdch" of the RC network is compared by the discharge time of the second in-bult RC network denoted as "tdchimo".
The two RC networks go through periodic charging by VDD(INTREGD) through a couple of identical and synchronized switch networks, and subsequently discharged with the help of a resistor to Vss or the ground
The rate at which this charge discharge is executed is regulated by a sampling rate denoted by "fs".
In case if the potential difference is seen to be dropping below the internally set reference voltage VM, the corresponding output of the comparator tends to become low. The logic level which follows the comparators identifies the exact comparator that actually could switch before the other.
And if the upper comparator is identified to have fired first, this results with a pulse being rendered on CUP, whereas if the lower comparator is detected to have switched prior to the upper, then the pulse is enabled at CDN.
The above pulses engage in controlling the charge level over the external capacitor Ccpc associated with pin CPC. When a pulse is generated on CUP, the Ccpc is charged through VDDUNTREGD for a given period of time which triggers a rising potential on Ccpc.
Quite on the same lines, when a pulse is rendered at CDN, the Ccpc gets linked with current sink device to ground which discharges the capacitor causing its potential to collapse.
Whenever the capacitance at pin IN gets higher, it correspondingly increases the discharge time tdch, which causes the voltage across the relevant comparator to fall at a correspondingly longer time. When this takes place the output of the comparator tends to get low which in turn renders a pulse at CDN forcing the external capacitor CCP to discharge to some smaller degree.
This implies that CUP now generates the majority of the pulses which causes CCP to charge up even more without going through any further steps.
Inspite of this, the automatic voltage controlled calibration feature of the IC which relies on a sink current regulation "ism" associated with pin IN makes an effort to balance out the discharge time tdch by referring it with an internally set discharge time tdcmef.
The voltage across Ccpg is current controlled and becomes responsible for the discharge of the capacitance on IN rather rapidly whenever the potential across CCP is detected to be increasing. This perfectly balances the increasing capacitance on input pin IN.
This effect give rise to a closed loop tracking system which continuously monitors and engages into an automatic equalizing of the discharge time tdch with reference to tdchlmf.
This helps to correct sluggish variations in capacitance across IN pinout of the IC. During rapidly charging sates for example when a human finger is approached the sensing foil quickly, the discussed compensation might not transpire, in equilibrium conditions the length of the discharge period do not differ causing the pulse to alternately fluctuate across CUP and CDN.
This further implies that with larger Ccpg values a relatively restricted voltage variation for each pulse may be expected for CUP or CDN.
Therefore the internal current sink gives rise to a slower compensation, thereby enhancing the sensitivity of the sensor. On the contrary, when CCP experiences a decrease, causes the sensor sensitivity to go down.
An in-built counter stage monitors the sensor triggers and correspondingly counts the pulses across CUP or CDN, the counter gets reset each time the pulse direction across the CUP to CDN alternates or changes.
The output pin represented as OUT undergoes an activation only when adequate number of pulses across CUP or CDN are detected. Modest levels of interference or slow interactions across the sensor or input capacitance does not produce any effect on the output triggering.
The chip makes note of several conditions such as unequal charge/discharge patterns so that a confirmed output switching is rendered and spurious detection are eliminated.
The IC includes an advanced start-up circuitry which enables the chip to reach equilibrium rather quickly as soon as the supply to it is switched ON.
Internally the pin OUT is configured as an open drain which initiates the pinout with a high logic (Vdd) with a maximum of 20mA current for an attached load. In case the output is subjected with loads over 30mA, the supply is instantly disconnected due to the short circuit protection feature which is instantly triggered.
This pinout is also CMOS compatible and therefore becomes appropriate for all CMOS based loads or circuit stages.
As mentioned earlier, the sampling rate parameter "fs" relates itself as 50% of the frequency employed with the RC timing network. The sampling rate can be set across a predetermined span by appropriately fixing the value of CCLIN.
An internally modulated oscillator frequency at 4% through a pseudo-random-signal inhibits any chance of interferences from surrounding AC frequencies.
The IC also features a useful "output state selection mode" which can be used for enabling the output pin to either in the monostable or bistable state in response to the capacitive sensing of the input pinout. It's rendered in the following manner:
Mode#1 (TYPE enabled at Vss): The output is rendered active for sp long as the input is held under the external capacitive influence.
Mode#2 (TYPE enabled at VDD/NTRESD): In this mode the output is alternately switched ON and OFF (high and low) in response to subsequent capacitive interaction across the sensor foil.
Mode#3 (CTYPE enabled between TYPE and VSS): With this condition the output pin is triggered (low) for some predetermined length of time in response to each capacitive touch inputs, whose duration is proportional to the value of CTYPE and can be varied with a rate of 2.5ms per nF capacitance.
A standard value for CTYPE for getting around a 10ms delay in mode#3 could be 4.7nF, and the maximum permissible value for CTYPE being 470nF, which may result in with a delay of about a second. Any abrupt capacitive interventions or influences during this period are simply ignored.
Reference: PCF8883 data sheet